| 摘要 |
PURPOSE:To optionally set a hysteresis characteris, and also to make it variable, by substituting an input resistance for a circuit which has connected a capacitor between a connecting point of 2 transfer gates and the reference potential, and controlling it by a clock signal. CONSTITUTION:A transfer gate TF1 controlled by a clock phi and a transfer gate TF2 controlled by antiphase of the clock phi are connected in series, and between the connecting point and the reference potential, a capacitor C is connected. Subsequently, 2 invertors IV1, IV2 are connected in series, the feedback is executed to the input point of the inverter IV1 through a resistance R2 from the output point of the invertor IV2, and also the output point of the transfer gate TF2 is connected to the input point of the invertor IV1. Also, by varying a period of the clock phi, the hysteresis characteristic is varied. |
