| 摘要 |
PURPOSE:To improve the system performance which increasing hit rate of high speed buffer memories, by providing two sets of high speed buffer memories for an operation processor and storing the memories at the same time in the storage of a job program to a storage device. CONSTITUTION:Two sets of high speed buffer memories are provided for an operation processor, and when a job program is stored in a storage device, the program is stored at the same time in one of the two high speed buffer memories. For example, when a program instruction is inputted to an input and output controller 1, the address information and data are given to the stroage device 2 via a storage contrller 3, the operation is discriminated at a command decoder 302 and the data is inputted to the operatiok processor 4 through a bus 305 via an area register 301 and a comparator 303. One of buses 305 and 306 is selected according to the content of a control register 401 with bus switches 403 and 404, and inputted data is stored to one of the high speed buffer memories 401 and 402 through the selected bus. |
