发明名称 PLL CIRCUIT
摘要 PURPOSE:To make circuit integration easy, by constituting a loop filter with three capacitors the charge/discharge of which is controlled with switches. CONSTITUTION:If the phase of an input signal (c) is delayed than that of an output signal (d) of a voltage controlled oscillator, a transistor Q1 turns on, the potential at an output terinal OUT is risen via a capacitor C2 and a TRQ10 turns on. As a result, the charge of a capacitor C1 is started and control is made so that the oscillated frequency of the voltage controlled oscillator can be increased according to the rise of the potential of the output terminal OUT. If the phase of the signal (d) is led, the potential of the output terminal OUT is decreased via a capacitor C3, a TRQ11 turns on and a charge in the capacitor C1 is discharged, to decrease the oscillated frequency.
申请公布号 JPS5827438(A) 申请公布日期 1983.02.18
申请号 JP19810126248 申请日期 1981.08.12
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA 发明人 ITOU AKIHIKO;SAITOU TADAHIRO;FUKUI HIROKAZU;IWATA ATSUSHI;KANEKO TAKAO
分类号 H03L7/093;H03L7/089 主分类号 H03L7/093
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