| 摘要 |
PURPOSE:To efficiently perform the advanced fetch of instruction through the addition of a fixed value to an adder calculating the next address with this output, by providing a cancellation signal and a cancellation FF. CONSTITUTION:When a readout microinstruction for the software instruction takes place, the content of an instruction address register 1 including the instruction up to now is added to an address adder 2 and the next software instruction is read out with the address set to a cancellation FF14. This readout address 3 is given to an address conversion circuit 4 together with an address readout request 6 to convert a logical address into a physical address. The number of bytes 7 of the readout request 6 is returned to a discrimination circuit 8 at the same time as the physical address of the next cycle converted at the circuit 4. The circuit 8 discriminates whether or not the request is cancelled with the number of present effective request bytes, number of bytes 11 picked up from an instruction register 10 for the software at the present cycle and a signal 12 representing the size and transmits the result to the circuit 4. |
