| 摘要 |
A FIFO system comprising an expandable number of identical FIFO chips identically interconnected to form a ring with each FIFO chip comprising a RAM memory with inboard and outboard pointing logic which, when activated, direct the writing or readout of words into or out of successive memory locations of each RAM. Each FIFO chip further comprises border transfer logic which connects each FIFO chip with the immediately preceding FIFO chip in the ring and is responsive to the writing or reading of a word into or out of the last memory location of the preceding FIFO chip memory to activate the inboard or outboard pointing logic, respectively, of each FIFO chip, and further is responsive to the writing or reading of a word into or out of the last memory location of each FIFO chip to deactivate the inboard or outboard pointer logic, respectively, of said FIFO chip.
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