发明名称 CYCLE SYNCHRONIZING SYSTEM OF LORAN C RECEIVING PULSE
摘要 PURPOSE:To elevate resolution of an A/D converter, and also to exactly measure an amplitude ratio even in case when S/N has been deteriorated, by deciding a synchronizing point due to the fact that a ratio of 2 continuous peak voltages of a receiving pulse attain about 1, by use of a variable gain amplifier. CONSTITUTION:A gain controlling circuit 6 is controlled through a CPU 7, and the gain of a variable gain amplifier 1 is switched to (k) times of a reference value becoming an amplitude ratio of 2 peaks of a synchronizing point as for the first peak among 2 continuous peaks of a receiving pulse, and to 1 time as for the following peak. Subsequently, 2 groups of continuous peak values are applied to the CPU 7, and when the amplitude value ratio of the continuous peaks becomes about 1, the CPU 7 decides the synchronizing point. According to this constitution by which the dynamic range has been multipled by (k) times substantially, resolution of an A/D converter is elevated substantially, also the amplitude ratio is measured exactly even in case when S/N has been deteriorated, and a cycle of a loran C receiving pulse can be synchronized without an error.
申请公布号 JPS5822977(A) 申请公布日期 1983.02.10
申请号 JP19810122306 申请日期 1981.08.04
申请人 FUJITSU KK 发明人 SUNAKAWA MITSURU
分类号 G01S5/10;G01S1/24 主分类号 G01S5/10
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