| 摘要 |
PURPOSE:To obtain a FET having high gains and high gm by forming source and drain regions while being contacted with an insulating layer with predetermined depth on an N type Si layer and shaping a gate region between both regions. CONSTITUTION:A P layer 3 is formed to a section, which is held by a SiO2 layer 2 having a predetermined space, of an N type substrate 1. The mutually parallel gate layer 4, source layer 5 and drain layer 6 are striately shaped to the P layer 3 while being contacted with the SiO2 layer 2. Gate wiring 7 is positioned onto the SiO2 2 and connects a pluraity of the gate layers 4, and a source electrode 8 connects the source layers 5. The P layer 3 is formed in thickness deeper than the insulating layer 2 and the gate, source and drain layers 4-6 in thickness shallower than the insulating layer 2. According to this constitution, wiring capacitance is extremely small because gate width increases equivalently by a plurality of the gate layers and the gate wiring 7 is positioned onto the SiO2 layer 2. Consequently, power gains and gm can be augmented only by enlarging the gate width. |
