发明名称 INTEGRATED CIRCUIT
摘要 PURPOSE:To endow with a self-testing function by a circuit wherein, in addition to a circuit block liable to fail, another circuit block having the same function as the former is provided in combination with each other. CONSTITUTION:A circuit unit 1 included a main circuit block 2 with the desired function and an auxiliary circuit block 3 with the same function as the block 2, both blocks having signal input terminals commonly connected. The unit 1 also includes exclusive logical addition gates 41-43 each as a comparative circuit which compares the corresponding two outputs from those circuit blocks 2, 3. When both circuit blocks 2, 3 are normal, all of the gates 41-43 assume ''0''. If either one of both blocks is failed, output of any one among the gates 41-43 assumes ''1''. Outputs from the gates 41-43 are input to a logical addition gate 5. If there is a failure in circuit units prior to the previous step, a stest input terminal 6 assumes ''1''. On the other hand, if there is no failure, the terminal assumes ''0''. This test input is introduced to the gate 5 together with the outputs from the gates 41-43, and an output terminal of the gate 5 constitutes a test output terminal 7 of the circuit unit 1.
申请公布号 JPS5821837(A) 申请公布日期 1983.02.08
申请号 JP19810120110 申请日期 1981.07.31
申请人 TOKYO SHIBAURA DENKI KK 发明人 HIRABAYASHI KANJI
分类号 H01L21/822;G01R31/316;H01L21/66;H01L21/82;H01L27/04 主分类号 H01L21/822
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