| 摘要 |
PURPOSE:To eliminate a malfunction in which plural memory cells are selected at one time, by using a buffer with which the level of the word line is set between the ground and the power supply voltage when the memory cells arranged in a matrix are selected. CONSTITUTION:An input part 1 supplies the signal fed from an X decoder, and an output part 2 delivers the signal to a word line. When a transmission gate of a memory cell part uses a load resistance 21 of a P channel MOSFET, the high level of the output can be reduced less than the power supply voltage. Thus the level of the word line is set lower than the when the memory cells are selected. As a result, the breaking time is decreased for the word line. The memory cells are not selected during the above-mentioned breaking time. Thus the simultaneous selection time is reduced for two memory cells, and the malfunction due to the simultaneous selection of the two cells can be eliminated. Otherwise an N channel MOSFET is also available along with the pull-down load resistance of the P or N channel MOSFET. |
