| 摘要 |
PURPOSE:To precisely synchronize respective devices with simple configuration without providing a specific priority controlling device. CONSTITUTION:A counter 120 is connected to a busy line 100 at its reset terminal and also connected to a pull-up power source through a resistor R1. An output of the counter 120 is inputted to a comparator 121, which generates an output Tc when the input coincides with a set value Cs. The output of the comparator 121 is inputted to the set terminal of a FF122. A using request Sreg is supplied to the reset terminal of the FF122. The Sreg is also supplied to an AND gate 123. The output terminal of the AND gate 123 is connected to the base of a transistor 124 and a gate of a data buffer 125 and the collector and emitter of the TR124 short-circuits the busy line 100. The output terminal of the comparator 121 is connected to a FF131 and an AND gate 132 and an output of the AND gate 132 controls a TR130, preventing an I/O10, which is a common source, from erroneous measurement when the I/O10 is made unexclusive for a period beyond a prescribed time. |
