| 摘要 |
PURPOSE:To improve the reliability of comparison and inspection to be performed by two microprocessors (processor), by operating them in such a way that one processor is later than the other processor by a fixed time. CONSTITUTION:A control signal (interrupt, reset, hold, etc.) to be inputted into a main processor MPA is inputted into a processor for comparison and inspection MPB after it is delayed by one clock cycle by a delay circuit D and the operation which is delayed for a fixed time is performed. Readout data RD to the processor MPA are latched by a register RDR and each signal of address, write data, and status outputted from the processor MPA is latched at registers AR, WDR, and SR by a strobe signal STBA, respectively. When each signal of address, write data, and status outputted from the processor MPB is outputted by another strobe signal STBB, they are compared with each output of the processor MPA, respectively, by comparators ER. |
