| 摘要 |
PURPOSE:To eliminate any error from the operation results by obtaining correct operation results from the initial value in terms of operations performed under the cooperation of a digital differential analyzer (DDA) and a multivariable function generating device (DDFG). CONSTITUTION:Control signal outputs LS2-LS4 and AND gates G1-G3 of a control memory MP are individually inserted, and, when a switch S is set to the off condition, each variable latching circuit LX, LY, and LZ do not make any holding operations because the control signal outputs LS2-LS4 and the AND gates G1-G3 are also set to the off condition and no gradient value is sent from a gradient value memory MG. Therefore, when a timing pulse generator TPG is operated under the condition where the switch S is set to the off condition before starting the whole arithmetic operation, an interval definition point memory MNB or a interval definition point controlling circuit DC, a variable memory MV, the control memory MP, the variable latching circuit LX, etc., of a multivariable function generating device (DDFG) operate, and a variable outputted from a register YR at a digital differential analyser (DDA) side is held by the variable latching circuit LX. Moreover, an approximate partition point in an interval definition point memory MN coincides with the outputted variable by the operations of the interval definition point memory MNB or the interval definition point controlling circuit DC. |
