发明名称 ARITHMETIC PROCESSING UNIT
摘要 PURPOSE:To easily judge the existence of an interruption request and to easily estimate the cause of abnormal operation of a program by writing a vector value indicating an interruption processing routine in a fixed address of a program memory. CONSTITUTION:A general register array 1 temporarily stores an arithmetic state and data processed by an arithmetic logic computing element 2. A program memory is controlled at its reading based on data written in respective addresses of a memory control circuit 5. An interruption control circuit 10 operates a vector table address in accordance with an interruption request inputted from an external apparatus and transfers the operated address value to a memory control circuit 5. An interruption vector holding circuit 11 to be used also as a vector value writing means writes a vector value inherent in each interruption request transferred to the circuit 5 by the circuit 10 in an inherent address of the memory 44.
申请公布号 JPS6349942(A) 申请公布日期 1988.03.02
申请号 JP19860192755 申请日期 1986.08.20
申请人 CANON INC 发明人 TAMURA NOBORU
分类号 G06F9/48 主分类号 G06F9/48
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