| 摘要 |
PURPOSE:To generate various synchronizing signals based on a reference clock signal and to output a frequency dividing output under a fixed phase relationship with the synchronizing signals, by deriving a horizontal synchronizing signal and resetting a frequency dividiing circuit for a fixed time when a power supply is turned on. CONSTITUTION:A horizontal and a vertical synchronizing signal HS and VS which are locked in phase to a reference clock signal from a quarts oscillating circuit 1 are generated by a synchronizing signal generating circuit 2 and the reference clock signal is divided into fractions of an integer by the 1st frequency dividing circuit 3, a PLL circuit 4, etc. The signals HS and VS from the circuit 2 are added to reset inputs of a horizontal and a vertical counter 6 and 7, respectively, and a picture memory 8 is driven by the outputs of the counter 6 and 7. An initializing circuit 10 is connected to the output side of the signal HS from the circuit 2 through a gate circuit 11 and the signal HS is passed by the circuit 11 only when a power supply is turned on. Then, the signal HS which passes through the circuit 11 is applied to the reset terminal of the circuit 3 and the divided output and the signal HS are set to have a fixed phase relationship. |
