| 摘要 |
PURPOSE:To improve the efficiency of utilization of a memory by varying a sampling period corresponding to an input waveform, storing a signal with less variation in less memory areas, and storing a signal with large variation in more memory areas. CONSTITUTION:An input is A/D-converted by a clock phis and stored temporarily in a register part 5 or 6. The clock phis has a period which corresponds to an input frequency and signals phiA and phiB are generated alternately synchronously with the clock phiS to operate corresponding to switched speeds. Up-to-date data of the register parts 5 and 6 and their last data are processed by an exclusive OR part 7, whose results are compared with a set value to decide on whether the amplitude exceeds the set input value or not. A comparison part 8 detects variation exceeding the set value to output a start signal for a high-speed period, and at the same time, indicates to a memory control part 3 to store the data in a memory part 4, and to output a flat storage signal. When variation less than the set value is detected, the control is returned to a characteristic period to stop the flag storage. |
