| 摘要 |
PURPOSE:To obtain an economical data channel device, by providing the memories that store the channel words using an input/output device in a time division way and in the number equal to the input/output devices which are actually used at one time. CONSTITUTION:A data channel device receives an input/output instruction from a CPU and then a control part 12 puts the data of IOA on a writing bus 13. This data is set to an IOA buffer 4. Then an idle bit position of an idle bit register 1 of a channel word CHW is detected by a detecting circuit 3, and the address of a CHW memory 9 is written into a CHW address memory 6. The contents of the memory 6 are read by a CHWA memory reading signal 8 to know the address of the memory 9, and 1 is written to the bit of the register 1 corresponding to the address of the memory 9. After this, the corresponding IOA is set to the buffer 4 with each reception of the data and then read and written out/into the memory 9. The transfer is controlled between an input/output device and a storage device by the contents of the memory 9. Accordingly it is not necessary to have the CHW memories equivalent to the maximum number of the input/output devices. |
