| 摘要 |
PURPOSE:To simplify the circuit and to attain the low power consumption and the improvement of reliability, by constituting a circuit with two D flip-flop circuits (D-FF) and two coincidence gate circuits. CONSTITUTION:When outputs (Q2,Q1) of D-FFs 2, 1 just before the application of clock pulses are (0,1), the level of output terminals X, Y, Z is respectively ''1'', ''0'', ''0'', and the said outputs (Q2,Q1) at the leading edge of a clock pulse C transfer to (0,0), and the level of output terminals X,Y,Z is respectively ''0'',''1'', ''0''. The outputs (Q2,Q1) are transferred to (1,1) at the leading edge of the 2nd clock pulse C, the output terminals X, Y, Z go to ''0'', ''0'', ''1'', respectively. The outputs (Q2,Q1) go to (0,1) at the leading edge of the 3rd clock pulse, the output terminals X, Y, Z go respectively to ''1'', ''0'', ''0'' and similar transition is repeated afterward. |
