| 摘要 |
Self-correcting, solid-state mass-memory, organized by bits and with reconfiguration capability for a stored program control system, comprising a processing system interfaced towards the mass memory through a controller, said memory consisting of one or a plurality of memory modules and a control module at least, comprising a time base which generates timing and control signals for memory operation, with shape and period variable according to the operation, an addressing control circuit which generates the addresses for memory reading and writing, input-output means which send the data towards the memory or the controller and a self-correcting logic which controls the right operation of the memory, corrects and signals to the controller the possible memory errors, said memory being characterized in that each memory module [ME(1)...ME(p); ME(1)...ME(p + 1); ME(1)...ME(x)] is intended to store a bit of a plurality of words consisting of information and redundancy bits to be used for self-correction operations and comprises:
- a plurality of memory integrated circuits (AC1...AC32) obtained by charge-coupled technology and consisting of blocks of shift registers organized in serial-parallel-serial configuration, each block being able to be addressed randomly and at the same time as the blocks of equal position in all the corresponding circuits of all the memory modules and containing a plurality of cells to be addressed in sequence;
- data input-autput means (RT1; RT1A; RT1B; RT1C; LM2);
- means (A1, A2, DE1, A!, A2, DE1, LM1) for receiving from the control module (MC) or each control module (MCA, MCB, MCC) and sending to the integrated circuits (AC) of the memory module the timing, addressing and control signals. |
