| 摘要 |
PURPOSE:To realize a device with enhanced integration while retaining a high withstand voltage capability by a method wherein a semiconductor is used with its principal plane parallel with the (100) or (511) axis and ring curvature radius is rendered larger, in the process of providing a guard ring enclosing an active region in an MOS type field effect transistor. CONSTITUTION:An N type semiconductor substrate 11 with its principal plane parallel with the (100) or (511) axis is coated with an oxide film 20 and is provided with a window with some distance from the P-N junction in the periphery of an element to be formed later. Next, by anisotropic etching, a V shaped groove 21 is created in the substrate 11 where it is exposed in the window, a window is provided again in the film 20, and a P type base region 12 is formed by diffusion or ion implantation. At the same time, a P type guard ring 13 is buried in the groove 21. In this way, the radius of curvature of the part A of the P-N junction constituted by the substrate 11 and the ring 13 is set at infinity, which is followed by conventional steps of forming an N type regions 14, P type base contact region 15, N channel region 16, and gate, source, drain electrodes 17-19. |
