| 摘要 |
PURPOSE:To easily perform high-speed data transfer, by alternately switching a part of a data memory of a CPU and a bus line of a data memory for an input and output device so that the data memory can be accessed from any of the CPU and the input and output device. CONSTITUTION:An address switching circuit 13, a data switching circuit 14 and a control switching circuit 15 are switched with the instruction of a CPU1 or an input and output device 5, and a data memory 3a is used as the data memory for the switched device. For example, when the memory 3a is used as the data memory for the device 5 and the circuits 13, 14 and 15 are switched to the CPU1 at the end of the storage of processing, the data of the device 5 can momentarily be transferred to the CPU1. |
