发明名称 INTERRUPTION SYSTEM FOR CENTRAL PROCESSOR
摘要 PURPOSE:To keep interruption processing ability, by saving the interruption from a register to a main storage device temporarily when the interruption takes place in excess of capacity of a register group used with changeover at the generation of interruption and processing the interruption afterward. CONSTITUTION:A CPU1 has an existing register group 2 and a save register group 3. While the CPU1 executes processing with the register 2, if an interruption request is given from a peripheral section 5, a register possible for use is selected out of the save register group 3 to switch the register with the existing register group 2 and the register group 2 is taken as the save register. If no register is available in the register group 3, the content which is changed over from the group 2 to the group 3 at the earliest time out of the group 3 is saved to a main storage device 4 for the replacement with the information relating to the interruption processing stored in the main storage section 4 in advance and the existing register group 2 before the time is taken as a part of the register 3. Thus, the interruption processing can be made efficient.
申请公布号 JPS5814253(A) 申请公布日期 1983.01.27
申请号 JP19810111967 申请日期 1981.07.17
申请人 NIPPON DENKI KK 发明人 YOSHIKAWA MITSUO
分类号 G06F9/46;G06F9/48 主分类号 G06F9/46
代理机构 代理人
主权项
地址