发明名称 MEMORY ACCESS CONTROL SYSTEM
摘要 PURPOSE:To decrease the time required for accessing, by determining the priority of memory access from a plurality of sub-processor groups and acessing the said memory access request to a memory directly from all the sub-processor groups. CONSTITUTION:Each information processing unit consisting of sub-proccessor groups 10A and 10B, system controllers 20A and 20B, and memories 30A and 30B forms two operation systems and can be operated as individual job, overall job and duplex systems. IF the systems are operated as one system job and a plurality of memory access requests come from 8 sub-processor systems 11A- 14A and 11B-14B, the controllers 20A and 20B discriminate the priority according to the predetermined priority and one memory access only is processed. Thus, the memory access time is decreased and the operation rate of the system can be improved.
申请公布号 JPS5814261(A) 申请公布日期 1983.01.27
申请号 JP19810111403 申请日期 1981.07.16
申请人 NIPPON DENKI KK 发明人 CHIWAKI YOSHINORI
分类号 G06F12/00;G06F13/18;G06F15/16;G06F15/177 主分类号 G06F12/00
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