| 摘要 |
PURPOSE:To improve the efficiency of utilization of an operating device, and to increase its arithmetic processing speed, by reading data out of an RAM in the former half of the arithmetic cycle of the operating device, and writing the data in the same address of the RAM in the latter half. CONSTITUTION:Data read out of an RAM1 in the former half of a clock supplied to an input terminal 11 is held in a register 2, whose contents are delayed by half the clock and held in a register 3. Fixed data read out of an ROM4 is held in a register 5. An operating device 6 performs arithmetic processing regarding the data signal from the registers 3, 5, and 7 by the arithmetic instruction from an instruction generator 9, and the arithmetic result is held in a register 7. In the latter half of the clock, one of the data from the registers 2, 3 and 7 selected by a switch 8, and data from an input terminal 10 is written in the RAM1, and the processed data is led out from an output terminal 12. |
