发明名称 PHASE LOCKING CIRCUIT
摘要 PURPOSE:To stably lock the phase of television signals and, at the same time, to obtain a circuit which is suitable for digitizing and integrating, by constituting a closed loop with an exclusive OR circuit, a transmission gate, and a divider. CONSTITUTION:An input signal A having a large duty ratio, such as a television synchronizing signal, is applied to a terminal 4 and supplied to one input of an exclusive OR circuit 1. On the other hand, a signal from a signal source, having a higher frequency than the input signal A and having the same frequency ratio as the input signal A, is applied to the 2nd signal input terminal 5, and two clock signals P1 and P2 having different frequencies are formed at a clock generating circuit 6 and supplied to a transmission gate 2. Since the frequency ratio between the input signal A and the clock signals P1 and P2 is almost constant and when the input signal A varies, the clock signals P1 and P2 also vary in the same way, an almost constant phase relationship can be maintained between the input signal A and the output signal B of a counter 3.
申请公布号 JPS5813074(A) 申请公布日期 1983.01.25
申请号 JP19810111787 申请日期 1981.07.16
申请人 MATSUSHITA DENKI SANGYO KK 发明人 CHIBA MITSUO
分类号 H04N5/93;H04N5/12 主分类号 H04N5/93
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