| 摘要 |
PURPOSE:To eliminate the need for a reception-side clock oscillator, and to remove restrictions from the Baud rate of transmission and reception, by synthesizing and transmitting a transmitted signal and a clock signal, and extracting data successively at a reception side by generated clock pulses with prescribed width. CONSTITUTION:Digital data recorded in a shift register 11 is read out by the 1st clock signal (b) and inputted to an NAND circuit 17 together with the 2nd clock signal (c). The output (d) of the NAND circuit 17 is inputted to an FF circuit 18 together with the 1st clock signal (b), and its output (e) and the 1st clock signal (b) are ORed by an OR circuit 19 to send a signal (f). At a reception side, the sent signal is inputted to a monostable multivibrator 23 tiggered at the rising point of the received signal, thus obtaining the 3rd clock signal (g). Then, the received signal is stored in a shift register 22 successively at rising points of the 3rd clock signal (g). |
