发明名称 |
COMPENSATING SYSTEM OF RECORDING TIMING |
摘要 |
<p>PURPOSE:To avoid the timing shift when a data is reproduced, by feeding a code word obtained by converting the data word which is used for the magnetic recording to a recording timing compensating circuit containing a shift register and a timing compensating means. CONSTITUTION:A data input 4 is obtained by converting a data word into a code word through a code converting circuit and has at least two bits ''0'' between a bit ''1'' and the next bit ''1''. Such data input is set at a flip-flop (FF) 19 with the timing of the clock 3 and then transferred successively to FF16- FF11. Then a data output 5 which is compensated for the timing through the delaying circuits 21-24, AND circuits 25-33 and an OR circuit 34 in accordance with the states of the FF19-FF11.</p> |
申请公布号 |
JPS5812115(A) |
申请公布日期 |
1983.01.24 |
申请号 |
JP19810110222 |
申请日期 |
1981.07.14 |
申请人 |
HITACHI SEISAKUSHO KK |
发明人 |
KAMEYAMA TADAHIKO;NAKAKOSHI KAZUO;HORIE TSUNEO;AOI MOTOI |
分类号 |
H03M7/14;G11B5/09;G11B20/14;H04L7/00 |
主分类号 |
H03M7/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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