发明名称 CONTROL PROCESSING SYSTEM
摘要 PURPOSE:To eliminate a failure of one control table from affecting on the other control table, by connecting an occupancy request line and an occpancy permission line to a common priority circuit through a microprocessor respectively provided to a plurality of control tables. CONSTITUTION:A microprocessor MPU is built in control tables 21-2n and they are connected to a device to be controlled 1 via a data bus 6 with the MPU for the giving/receiving of data. Each control table is connected to the priority circuit 5 with occpancy request lines 71-7n and occupancy permission lines 81-8n mutually. The circuit 5 discriminates the priority with the occupancy request signal from each MPU through the use of the software for the interlocking of operation information and when the device 1 is occupied with a specific control table for a prescribed time or more, an alarm is generated. The MPUs are decentrarizingly located for each control table and the interlocking is constituted witb the software, allowing to avoid a failure of a control table from being affected on the other control tables.
申请公布号 JPS5812051(A) 申请公布日期 1983.01.24
申请号 JP19810110428 申请日期 1981.07.15
申请人 TOKYO SHIBAURA DENKI KK 发明人 KURODA SATOSHI
分类号 G06F13/14;G06F9/00;G06F9/46;G06F11/00;G06F15/16;G06F15/177 主分类号 G06F13/14
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