| 摘要 |
PURPOSE:To speed up a storage instruction processing of a pipeline control, by detecting whether or not the succeeding instruction of an instruction with write operation has memory access operation, and waiting for the processing of succeeding instruction by one machine cycle accordingly. CONSTITUTION:When an instruction just after the instruction with write operation is an instruction requiring the memory access to a cash memory 12 with a detection circuit 36, a CNT 40 switchingly controls gates 321 and 322 each output of control flag registers 21 and 22 can not be transmitted to a read flag register (RC)26 and a write flag register (1st WC)33 at the next machine cycle. Further, the transfer to control flag registers 21,22 and 23, a logical address register 20 and control flag registers 16,14 and 15 located at the former stage than the RC26, the 1st WC33, a (CC)28 and a physical address register (1st AP) is temporarily stopped. |
