| 摘要 |
PURPOSE:To eliminate waiting of main storage operation by making operation so that when all blocks of n-column corresponding to mi-row are invalidated, all blocks of n-column corresponding to mi+1 row are invalidated. CONSTITUTION:The contents of a stop address register are made number of sets + L (length of a line), and inputted to an input terminal of a comparator 8. On the other hand, the contents of an effective address register 1 are made all ''0''. The prefetch baud 10 inputs address to an adder 11 which is at input of the address register 1. When there is carry from the line address, page address is increased by 1. By this, set position that becomes an object of operation is sent out to a set register 12 and an object set is designated to address array 3 and a buffer 6 by a decoder circuit 4. When this operation is repeated for the number of stes + L, it is detected by a comparator 8 and buffer invalidation operation comes to an end. Thus, waiting of main storage operation can be eliminated. |
