| 摘要 |
PURPOSE:To reduce the error of a byte synchronizing clock and at the same time to eliminate disorder of byte synchronism, by producing the byte synchronizing clock with use of a framing code and its preceding clock line. CONSTITUTION:The wave detection output of a wave detecting circuit 13 is supplied to a gate circuit 421, and at the same time a pulse P42 showing the signal period of the character broadcast is supplied to the circuit 421 as a control signal. A packet PCT is extracted out of the circuit 421. This PCT is supplied to a shift register 422 of the serial input and parallel output of 12 bits for example as well as to a PLL423. Thus a clock BITC having the bit synchronism is produced and supplied to the register 422. The AND circuits 424 and 425 plus an NOR circuit 426 are provided as decoders. The outputs QC-QL of the register 422 are supplied to the circuit 424; and the outputs QA-QK of the register 422 are supplied to the circuit 426. The outputs of the circuits 424 and 426 are supplied to the circuit 25. |
