发明名称 JITTER SUPPRESSING PHASE CONTROL CIRCUIT
摘要 PURPOSE:To decrease the number of circuits using great number of flip-flops, by delivering an output clock after varying the oscillating frequency of a voltage control oscillator so as to reduce the phase difference voltage nearly to zero. CONSTITUTION:A phase comparator 15 compares a clock of a long cycle given from a frequency divider 13 with a clock of a long cycle given from a fist-in/ first-out circuit 14 and delivers an output corresponding to the difference of phases of the above-mentioned clocks. The voltage corresponding to the phase difference and delivered from the comparator 15 is fed to a voltage control oscillator 17, and the pulse oscillating frequency is controlled so as to reduce the voltage corresponding to the phase difference nearly to zero. The output of the oscillator 17 is used as a reading clock to obtain an output clock (c), and as a result the entire circuit forms a PLL system. Then the jitter contained in an input data (b) and an input clock (a) is suppressed with an output data (d) and an output clock (c).
申请公布号 JPS589455(A) 申请公布日期 1983.01.19
申请号 JP19810106244 申请日期 1981.07.09
申请人 NIPPON DENKI KK 发明人 HAYASHI KUNIYASU;ASANO HIROSHI;KURITANI KAZUNARI
分类号 H04J3/07;H03L7/08;H04L25/05 主分类号 H04J3/07
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