| 摘要 |
PURPOSE:To minimize the reduction in processing ability, by separating a bus for direct memory access from buses for CPU access and controlling the logical connection of a memory bank in the bank unit. CONSTITUTION:A system bus control circuit 1 makes a system bus detecting circuit 2 effective when a memory access request signal 12 from a CPU is set, and when a memory bank which is being accessed with the CPU is not in a memory access DMA, a system bus state signal 18 is set. On the other hand, a DMA control circuit 3 is started when a DMA request signal 14 from an I/O having the DMA bank detection signal is set to make the DMA bank detection circuit 4 effective. When the CPU is not accessed, the circuit 3 sets a DMA bus state signal. A memory bank control signal generating circuit 35 logically connects the memory bank instructed with the circuit 2 when the signal 18 is set and the DMA bus with the circuit 4 when the signal 19 is set. |
