| 摘要 |
PURPOSE:To remarkably increase the transfer speed of block data, by accessing each file memory in parallel with a DMA channel and performing data transfer between the DMA channel and a main memory in time division from the result of access. CONSTITUTION:Starting is performed from a CPU 6 to DMA channels 31 and 32. In starting, the channels 31 and 32 access data, which are transferred to a main memory 1 with a transfer occupying time of a bus 4. The transfer of data is executed by the channel accessed earlier to request bus occupying right to a bus controller 5. After the transfer rate of file memories 21 and 22, the succeeding data are accessed in each file in parallel and transferred to the memory 1. When the memories 21 and 22 are magnetic bubble memories, in the transfer operation, no complete synchronizing operation is performed, but each data is surely transferred to the address of the memory 1 indicated with main memory address registers 71 and 72 by using the bus 4 in time division, allowing to remarkably reduce the entire transfer time. |
