发明名称 SYNTHESIZER RECEIVER
摘要 PURPOSE:To enable automatic channel selection with the output signal of a delay circuit, by providing the delay circuit which gives a delay for a given time to the output signal of a comparator, and controlling the generation of automatic stop signal with the output signal of a circuit 20. CONSTITUTION:The output signal of an IF filter 5 is fed to the input side of a buffer amplifier 10, and the output of the amplifier 10 is detected at 17 and fed to one input terminal of a comparator 18. The reference voltage VS of a reference power supply 19 is given to another input terminal of the comparator 18. Further, the signal obtained at the output of the comparator 18 is fed to one input terminal of an AND circuit 14 via a variable delay circuit 20. In this case, the delay time of the circuit 20 is varied from the time when the signal level fed from the output of the circuit 17 to one input terminal of the comparator 18 is greater than the voltage VS to the time when the reception frequency is sequentially changed and the signal level is maximum. The output signal of the circuit 20 controls the production of the automatic stop signal. Thus, automatic channel selection can be made at an accurate tuning point.
申请公布号 JPS56109025(A) 申请公布日期 1981.08.29
申请号 JP19800010673 申请日期 1980.01.31
申请人 SONY CORP 发明人 IIDA KAZUMI
分类号 H03J7/28;(IPC1-7):03J7/28 主分类号 H03J7/28
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