| 摘要 |
PURPOSE:To prevent malfunction due to variation in power voltage, etc., even if the values of a capacitor and a resistance are increased so as to reduce the influence of the rising time of the power voltage, by connecting an MOS transistor (TR) in parallel to the resistance. CONSTITUTION:When a power voltage is applied between power terminals 10 (VDD) and 11 (VSS), the voltage at the connection point 14 of a capacitor 12 and a resistance 13 approaches from VSS to VDD as the power voltage rises and then falls gradually down to VSS, but when it reaches the inversion level VT of an inverter 15, the voltage at its output terminal is inverted from VSS to VDD to turn on an MOSTR16 with relatively low in resistance, and thus the value of the resistance between the connection point 14 and power terminal 11 is decreased to lower the level at the connection point 14 to VSS rapidly. The time up to the inversion of the inverter 15 depends upon the capacitor 12 and resistance 13 and after a setting pulse is outputted temporarily to invert the inverter 15, the MOSTR16 held in the on state holds the connection point 14 at VSS. |
