| 摘要 |
PURPOSE:To quickly and simply restore the system-down due to parity error, by writing an address and a data of the address of a memory at failure to an address register and a data register. CONSTITUTION:When a data is written in a memory 2 and a parity error takes place, the parity error is stored to the 1st parity error storage circuit 8 via a parity check circuit 7 and the failure of the memory 2 is reported to a controller 1. Simultaneously, the address is written in an address register 4 via the circuit 8. At the re-operation via the controller 1, if the address of the register 4 is coincident with the address from the controller 1, a memory control 3 selects a 1-byte register 6 via an address comparison circuit 5 and the data in the address is stored in the register 6. The 2nd parity storage circuit 9 is made active via the circuit 8. Thus, the system-down due to the generation of parity error can quickly and simply be restored without memory exchange. |
