发明名称 COMMUNICATION SYSTEM BETWEEN PROCESSORS
摘要 PURPOSE:To directly start a processing from an address to simplify a processing stage by providing plural interruption generation registers corresponding to interruption levels between processors and setting the address for routines which should be processed to the said registers. CONSTITUTION:To the interruption generation register 5 or 6, the address for processing routine of the event to be processed is set from a processor 1 or 2, so the interruption occurs in the processor 1 or 2 with a specified interruption level. The processor 1 or 2 which receives the interruption can directly jump to the processing routine of the event to be processed by the address of the interruption generation register 5 or 6. Therefore, by setting the address of the processing routine instead of setting an event code, the processor 1 or 2 can directly jump to the event processing routine with omitting the processing stage which the processor 1 or 2 conventionally needs, such as the occurrence of the interruption, the jump to the routine for interruption and the analysis of the event code.
申请公布号 JPS6359649(A) 申请公布日期 1988.03.15
申请号 JP19860204368 申请日期 1986.08.29
申请人 FUJITSU LTD 发明人 ONUMA SHUNICHI
分类号 G06F15/16;G06F15/17;G06F15/177 主分类号 G06F15/16
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