| 摘要 |
PURPOSE:To shorten the processing stopping time of a logic simulator accompanying an output vector calculation by providing a means to process a logic in which the logic simulator is except an actual chip while an actual parts interlocking device obtains the output vector of the actual chip. CONSTITUTION:A logic simulator 100 conveys an output vector read from an actual parts interlocking device 300 to a logic connected to respective output pins of a chip 101 based on output delaying times t1-t3 of respective pins theta1-theta3 of a chip described in a text file 200. Consequently, out of the output delay time of respective pins of the chip described in the file 200, up to the minimum delay time, the influence of the output vector is not conveyed to the logic except the chip. Consequently, the logic except the chip can be simulated without an output vector. UP to the minimum delaying time described in the file 200, the logic except the chip can be simulation-processed in parallel to the output vector calculating processing at the device 300. |
