发明名称 TESTING METHOD FOR ERROR PATE
摘要 PURPOSE:To remove inevitable and temporary hindrance occuring in a testing device by continuing retesting automatically when errors more than the allowable error number take place, and thereby averaging temporary deflection of error factors. CONSTITUTION:Simultaneously when the content of a test sample counter 3 is renewed through the intermediary of a test executing unit 1, a gate is controlled and thereby the content of an error counter 2 is renewed. A decision starting unit 7 controls a gate circuit when the content of the counter 3 reaches a prescribed value of an output of a sample specifying register 5, and it generates a good decision signal when errors identified by a decision unit 6 are less than an allowable number. When an error rate exceeds the allowable number, a retesting execution signal is generated until the content of a retesting register 9 subtracted sequentially by a retesting decision unit 8 turns to be zero, and thereafter a badness signal is generated. By the continuation of this retesting, temporary deflection of error factors other than a testing device is averaged, thereby temporary hindrance occuring in the testing device is removed, and thus the decision of badness due to inevitable unstability elements generated in the testing device is eliminated.
申请公布号 JPS585675(A) 申请公布日期 1983.01.13
申请号 JP19810102940 申请日期 1981.06.30
申请人 FUJITSU KK 发明人 MIYAHARU YOSHINORI
分类号 G01R31/26;G01R31/00;G01R31/28 主分类号 G01R31/26
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