| 摘要 |
PURPOSE:To allow one circuit to have various column converting functions by supplying outputs of all series-parallel converters to respective data selectors, and controlling the respective data selectors with individual selection signals. CONSTITUTION:M Trains of input signals supplied to input terminals 20-1-20-M are converted by M units of series-parallel converters 40-1-40-M into N trains of parallel signals, which are supplied to data selectors 50-1-50-N respectively. The data selectors 50-50-N select the signals with selection signals from a selection signal generator 63. A clock signal is frequency-divided by a factor N through a frequency dividing circuit 60 to control parallel-series converters and the output of the frequency dividing circuit 60 is multiplied by a factor M, and then frequency-divided by the factor M through a frequency dividing circuit 62. The selection signal generator 63 generates selection signals S1-SN for respective data selectors according to the frequency division phase of the frequency dividing circuit 62. The M trains of input signals inputted to the input terminals 20-1-20-M are outputted as N trains of output signals to output terminals 30-1-30-N. |
