发明名称 PUSH-PULL TYPE MOS LOGICAL CIRCUIT
摘要 PURPOSE:To effectively use a chip area, by reducing the number of signal wires through the constitution of all or a part of logical inputs with true inputs and complement inputs and decreasing the area in which the signal wiring is occupied in the integrated circuit. CONSTITUTION:An input A of a logical block in an integrated circuit is applied to the gate of an N type MOS transistor(TR) TR3 of a non-push-pull type inverting circuit 2 of a three-input NOR circuit 1 and inputted to the gate of a driving MOS TR4 of the circuit 1. The drain of the TR3 is connected to the gate and the source of an N type MOS TR5 and the drain of the TR5 is connected to a power supply Vcc. The source of the TR4 and driving MOS TRs 6 and 7 are connected to a reference potential, a common connection point 8 of them is used as an output terminal 9, a series circuit of load MOS TRs 10-12 is connected to the connection point 8, and an output -A of the circuit 2 is inputted to the gate of a TR12. Other logical inputs B and C are applied to the gate of the TRs 6 and 7 and complement logical inputs -B and -C are applied to the gate of the TRs 11 and 10.
申请公布号 JPS583327(A) 申请公布日期 1983.01.10
申请号 JP19810101119 申请日期 1981.06.29
申请人 FUJITSU KK 发明人 NISHIUCHI KOUICHI;TAKAHASHI HIROMASA
分类号 H03K19/0944 主分类号 H03K19/0944
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