| 摘要 |
PURPOSE:To improve the reduction in a linear region of a phase comparison characteristic through the reduction in set and reset width, by feeding back an output of a phase comparison circuit repeating set/reset to a pulser generating a set and a reset pulse. CONSTITUTION:A digital phase synchronizing circuit is provided with FFs 1, 2 and 3 of set/reset type and gates GATE1 and 2 taking logic of two inputs, and the FF1 is set when a clock 1 goes to an L level and the FF1 is set when the level goes to an H with an output 5 of the GATE1. An output 8 of the FF1 is fed back to the FF2, and the FF2 is reset when the FF1 is set and an input 3 of the GATE1 goes to the L level. The operation of an input signal 2 for the FF3, GATE2 and the FF1 is performed similarly. The set/reset width is reduced, a pulse width sufficiently for the circuit operation is generated and the reduction in the linear region of the phase comparison characteristics can be minimized. |
