发明名称 DETERMINING SYSTEM FOR INTERRUPT PRIORITY LEVEL
摘要 PURPOSE:To improve a processing speed practically, by controlling the allowable queuing time by a hardware in the real-time processing system using a microprocessor. CONSTITUTION:When interrupt inputs (a)-(c) come, corresponding counter parts 5-7 are preset to respective allowable queuing times in accordance with these interrupts. Then, an interrupt generating part 8 transmits information to a central processing part so that the central processing part executes the processing for the interrupt which corresponds to one of counters 5-7 to which the shortest queuing time is set. After the processing is terminated, this corresponding counter is reset and is not operated until the next interrupt. Consequently, when plural interruption causes exist, the interruption processing is executed effectively in respect to time.
申请公布号 JPS582952(A) 申请公布日期 1983.01.08
申请号 JP19810101098 申请日期 1981.06.29
申请人 FUJITSU KK 发明人 TANIGUCHI YOSHIHIKO;OOTA KOUICHI;SUZUKI HAYASHI
分类号 G06F9/48 主分类号 G06F9/48
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