| 摘要 |
PURPOSE:To eliminate an effect due to an increment of the number of interleaves, by giving a simultaneous access to all interleaves in the refresh mode and refreshing the cells in each memory element with each line. CONSTITUTION:A main memory MS of 256MB capacity (MB: megabyte) is divided into 256IL (IL: interleave). In this case, 1IL has 8B (B: byte). The access throughput to be given to the memory MS from a memory control unit MCU has 8BX8 megacycle. Each memory access controller MAC controls 32IL. Then 256ILX8BX2 is refreshed all at once. With a refresh action, the unit MCU starts the refresh at one time to the controllers MAC#0-#7. Thus each MAC refreshes 1IL of all RAM elements of 32ILX8BX2 which are connected to the own MAC. In this case, the MCU inhibits an access to the MS until the BUSY state caused by the refresh is released. |
