| 摘要 |
PURPOSE:To decrease the access time, by dividing a memory cell array into blocks and setting a parallel-series converting circuit to deliver the output in series from each block. CONSTITUTION:A memory array 100 is divided into blocks 100-1-100-4. An address buffer circuit 4CA produces the internal address signals 14CA and 14CA' in the rise mode of an address buffer control signal 12 which is generated in response to a column selection control clock signal 1C. In response to these internal address signals, a bit line selecting circuit 5CA selects a bit line pair with each blocks 100-1-100-4 and feeds the signal to the data line pairs I/01- 4. These signals are supplied to a selecting circuit 201 respectively. On the other hand, a decoder 5ZS selects a line Z1 in accordance with the output of an address buffer 4C's. Then the output of a circuit 6C1 is selected and supplied to an output amplifying circuit 7CS to be delivered to a terminal 8. When the operation of a circuit 7CS is over, the next column address is supplied via a line 3 to repeat the same operation. |
