| 摘要 |
PURPOSE:To enable to enlarge the scale of gate arrays by a method wherein con duction paths made of the gate electrode material of an FET are arranged in proximity to basic cells, and the wiring is composed of wiring layers provided on basic cell arrays and the conduction paths and the conduction paths. CONSTITUTION:The basic cells BC and the conduction paths LG are alternately arranged. For example, these conduction paths LG are formed in the wiring channel region in array form by the same process as that of a gate electrode by the use of the same conductor layer as that of the gate electrode of the MOSFET the basic cell. The conduction paths LG can be provided approx. in four pieces of the maximum to a piece of basic cell, and the conduction paths are electrically isolated from each other, and the conduction paths are electrcially isolated from the basic cells. The conduction paths can be processed by being cut to length reaching inside the basic cells as the input-output terminals of the unit cell inner wiring. Otherwise, the connection can be processed as the unit cell outer wiring by termination outside the basic cell region. |
