| 摘要 |
In data transmission systems in which data is sent in binary bit streams (eg using HDLC format) and the clock at the receiver is derive from, or synchronised to, the change, eg from 0 to 1, in logic state in the incoming bit stream, the bits as they go out also go into a n bit shift register (SR) whose contents are monitored by an OR gate (01) detecting n 0 bits (eg n is between 2 and 8). When such a condition is detected, sending is delayed while a 1 bit is inserted after the nth 0 bit. At the receiver, the incoming bits go into an (n + 1) bit shift register whose contents are monitored by gating means for the combination of n 0 bits followed by a 1 bit. When this condition is detected, that 1 bit is detected. The added 1 bit, used in conjunction with HDLC code driving a phase locked loop oscillator (PLO), ensures that sync. is not lost because of a long string of 0 bits. At the receiver there is a further monitoring for (n + 1) successive 0 bits: if this is detected, an error indication is given. <IMAGE> |
