CONTROL SYSTEM FOR INTERLOCK CONDITION

摘要

PURPOSE:To provide a margin for time to the transfer of interlock condition, by inserting a buffer register not relating to a pipeline processing between a plurality of instruction registers. CONSTITUTION:A buffer register 7 not relating to a normal pipeline processing directly is inserted between instruction registers 2-1 and 2-2. A transfer bus is provided from the instruction register 2-1 and the register 7 for the register 2-2. A gate signal directly controls an input terminal gate 4-1 of the register 7 and an input terminal gate 4-2 of the register 2-2. The instruction transfer route from the register 2-1 is switched to the register to the register 2-2 and control of the gate 4-1 of the register 2-1 is made based on the instruction set to the register 7.