| 摘要 |
PURPOSE:To guarantee the retrial without malfunction even with interruption, by operating a plurality of operation processing devices in parallel and arranging the notice of completion of execution of instruction in the order of program even if the order of execution of instruction is in disorder at a data processor. CONSTITUTION:A fetch register 10 fetches an instruction information train sequentially read out from a main storage device and the content is written in waiting registers 12 and 13. In this case, an instruction order number ID is added to each instruction with an instruction number providing circuit 14. The registers 12 and 13 are selected with a selector 16 at each one cycle and the condition of instruction transmitting control is checked with an instruction transmission control circuit 17. When this instruction is a vector addition instruction VA, this instruction is transferred to a storage register 19 during the exeuction of operation and if the instruction is a vector multiplication instruction MA, this instruction is transferred to a storage register 19 during the execution of operation. Thus, fetch of the completed instruction from the registers 19 and 22 is performed in the order of the number ID. |
