| 摘要 |
PURPOSE:To shorten the time difference between two outputs of a logical circuit which has complementary outputs, by arranging output transistors (TR) at the emitter and collector of an input TR. CONSTITUTION:Although the output of a TTL circuit is inputted to an inverter heretofore to obtain complementary outputs, the 2nd npn output TRT3 is connected to even the collector of an inout pnp TR in this invented circuit. Then, the output signals are lead out of the collectors of the TRs T2 and T3. Consequently, the outputs O1 and O2 are the complementary outputs and the time difference between the outputs are very less. |
